1. Field of the Invention
This invention relates to a semiconductor device and a manufacturing method therefor, and more particularly to a device isolation film and a MIS transistor that is formed on a device formation region of one major surface of a semiconductor substrate surrounded by the device isolation film.
2. Description of the Related Art
FIGS. 65 and 66 show a MIS transistor (an N-type MOS transistor in this example) formed on a device isolation film formed by a well known LOCOS method and in a device formation region on one major surface of a semiconductor substrate surrounded by the device isolation film. In the drawings, reference numeral 101 designates a semiconductor substrate consisting of a silicon substrate having a first conductivity type (a P type conductivity in this example), and reference numeral 102 designates a device isolation film which is made of a silicon oxide film and is formed on the device isolation region of the semiconductor substrate so as to surround the device formation region. The device isolation film is formed by forming a silicon nitride film so as to cover the device formation region, and by selectively oxidizing a part of the device formation region uncovered with the silicon nitride film, i.e., only the device isolation region by exposing the device formation region to an oxidizing atmosphere.
Reference numerals 103 and 104 are a pair of source/drain regions, and they are formed in the device formation region of the semiconductor substrate 101 surrounded by the device isolation region 102 in such a way as to be separated from each other with a channel region 105 being sandwiched between them. The source/drain regions 103 and 104 are formed by impurity regions having a low impurity concentration 103a and 104a, and high impurity concentration regions 103b and 104b. Reference numeral 106 is a gate electrode formed on the channel region 105 with a gate oxide film interposed between them, and the gate electrode 106 is integrally formed together with a gate electrode wiring layer 111 formed on the device isolation film 102. Reference numerals 108 and 108 are side walls (side wall insulation films) formed on the side surfaces of the gate electrode 106, and the side walls 108, 108 are utilized as a part of a mask used in forming the high impurity concentration regions 103b and 104b of the pair of source/drain regions 103 and 104.
Reference numeral 109 is an interlayer insulation film, and this interlayer insulation film is formed over the device isolation film 102, the pair of source/drain regions 103 and 104, the gate electrode 106, and the side wall insulation films 108. Contact holes 109a and 109b are formed in this interlayer insulation film 109 so as to respectively communicate with the pair of source/drain regions 103 and 104. Reference numerals 110a and 110b are a pair of source/drain electrodes which are electrically connected to respective the pair of source/drain regions 103 and 104 through the contact holes 109a and 109b of the interlayer insulation film 109. A MOS transistor is made by the pair of source/drain electrodes 110a and 110b, the pair of source/drain regions 103 and 104, and the gate electrode 106.
For the device isolation film 102 formed by the LOCOS method, a part of the device isolation film 102, which is in contact with the device formation region of the semiconductor substrate 101, is gently tapered. By virtue of this gently tapered portion, it is possible to easily form a wiring layer around the tapered portion, that is, the gate electrode wiring layer 111 integrally formed with the gate electrode 106, without the necessity of taking into consideration the influence of a step, as shown in the drawing. However, in general, there arises a bird's beak geometry of 150 nm or thereabouts. This bird's beak geometry causes a mask size of the device formation region of the semiconductor substrate 101 to become narrower or smaller when compared with the size of the same in a photolithographic mask at the time of the formation of the device isolation film 102.
As shown in the drawings, if the device formation region is narrow, the contact holes 109a and 109b will be different from desired locations, for example, the center positions of the source/drain regions 103 and 104 because of the misalignment of the mask, the contact hole 109b will be formed at the edge of the device isolation film 102 when the contact holes 109a and 109b are formed in the interlayer insulation film 109. At this time, the semiconductor substrate 101 and the source/drain region 109b are short-circuited by the source/drain electrode 110b, and the device may not function as the MOS transistor.
To prevent this, it is necessary to make the size of the source/drain regions 103 and 104 larger by only a dimension of an alignment accuracy (a finite value) determined by the performance of an exposing apparatus which carries out photolithography, that is, a dimension la shown in FIG. 65. In other words, it is necessary to ensure sufficient distances between the contact hole 109a and the edge of the device isolation film 102 and between the contact hole 109b and the edge of the device isolation film 102 when the device is designed. This requirement hinders the high integration of a semiconductor integrated circuit device, in other words, the miniaturization of the device formation region.
When the gate electrode 106 is formed, or patterned, it is necessary for both ends of the gate electrode 106 to reliably stretch over the device isolation film 102, as shown in FIG. 66. If clearance is formed between the edges of the gate electrode 106 and the device formation film 102, ions will be also implanted into the clearance when the pair of source/drain regions 103 and 104 are formed in a self-aligned manner using the gate electrode 106 and the device isolation film 102 as a mask. As a result of this, the pair of source/drain regions 103 and 104 are electrically short-circuited, and the device fails to operate as a transistor.
As shown in FIG. 66, to prevent the electrical short-circuit between the pair of source/drain regions 103 and 104, it is necessary to ensure a dimension lb between the edge of the device isolation film 102 and the edge of the gate electrode 106 laid on the device isolation film 102, as a design margin when the device is designed. This design margin also serves as another factor to prevent the high integration of the device.